Design & Implementation of a Superscalar Processor

In Fall 2003, I took a Superscalar Processor architecture course at The University of Texas at Austin. For a group project, my group decided to design and implement (in synthesizable Verilog) a 2-way superscalar pipelined processor.

Why did we want to do that? Our main goal was to gain real-world experience of the methodology and problems faced in the corporate world. Secondly, the project provided quite an exercise in large-scale project management.

We started out with a formal procedure for determining the number of stages of a scalar pipelined processor. After a verified implementation had been finished, we then proceeded to effectively 'double' much of the logic in order to create a 2-way superscalar processor. (Well, we did have a lot more data-dependency checking to perform).

The source code for the project was approximately 100 Kbytes of pure RTL fun (~70 pages of small text), all typed by hand. This was no small project.

For verification, we wrote many test programs and thought of creative ways to test various forseeable aspects. For short programs, we watched every cycle to see that things were changing as they should. We also wrote some fairly complicated routines and verified the memory dumps for correct operation.

Looking back, I wish I known about the Vera language and randomized testbench design, as I later learned during my internship at SigmaTel.

We had also constructed a scalar, non-pipelined processor. The report also contains benchmarking data and comparisions between all three processors.

Please see the links at below for the full report.

Report [PDF]
Report [HTML]